CD4001UB-MIL Series

Military 4-ch, 2-input, 3-V to 18-V NOR gates

Catalog

Military 4-ch, 2-input, 3-V to 18-V NOR gates

Part	Supplier Device Package	Number of Circuits	Number of Inputs	Max Propagation Delay @ V, Max CL	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Quiescent (Max) [Max]	Input Logic Level - Low [Min]	Input Logic Level - Low [Max]	Package / Case [custom]	Package / Case [custom]	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Logic Type	Input Logic Level - High [Max]	Input Logic Level - High [Min]	Operating Temperature [Min]	Operating Temperature [Max]	Package / Case [x]	Package / Case [y]
Texas Instruments CD4001BPWR	14-TSSOP	4	2	90 ns	Surface Mount	3.4 mA	3.4 mA	1 çA	1.5 V	4 V	0.173 "	4.4 mm	14-TSSOP	18 V	3 V	NOR Gate	11 V	3.5 V	-55 °C	125 °C
Texas Instruments CD4001UBMT		4	2		Surface Mount	3.4 mA	3.4 mA	1 çA	1 V	2.5 V			14-SOIC	18 V	3 V	NOR Gate	12.5 V	4 V	-55 °C	125 °C	0.154 in	3.9 mm
Texas Instruments CD4001UBM96		4	2		Surface Mount	3.4 mA	3.4 mA	1 çA	1 V	2.5 V			14-SOIC	18 V	3 V	NOR Gate	12.5 V	4 V	-55 °C	125 °C	0.154 in	3.9 mm
Texas Instruments CD4001BMT		4	2	90 ns	Surface Mount	3.4 mA	3.4 mA	1 çA	1.5 V	4 V			14-SOIC	18 V	3 V	NOR Gate	11 V	3.5 V	-55 °C	125 °C	0.154 in	3.9 mm
Texas Instruments CD4001BM		4	2	90 ns	Surface Mount	3.4 mA	3.4 mA	1 çA	1.5 V	4 V			14-SOIC	18 V	3 V	NOR Gate	11 V	3.5 V	-55 °C	125 °C	0.154 in	3.9 mm
Texas Instruments CD4001UBF3A
Texas Instruments CD4001UBNSR	14-SO	4	2		Surface Mount	3.4 mA	3.4 mA	1 çA	1 V	2.5 V			14-SOIC	18 V	3 V	NOR Gate	12.5 V	4 V	-55 °C	125 °C	0.209 "	5.3 mm
Texas Instruments CD4001UBPWR	14-TSSOP	4	2		Surface Mount	3.4 mA	3.4 mA	1 çA	1 V	2.5 V	0.173 "	4.4 mm	14-TSSOP	18 V	3 V	NOR Gate	12.5 V	4 V	-55 °C	125 °C
Texas Instruments CD4001BNSR	14-SO	4	2	90 ns	Surface Mount	3.4 mA	3.4 mA	1 çA	1.5 V	4 V			14-SOIC	18 V	3 V	NOR Gate	11 V	3.5 V	-55 °C	125 °C	0.209 "	5.3 mm
Texas Instruments CD4001BM96		4	2	90 ns	Surface Mount	3.4 mA	3.4 mA	1 çA	1.5 V	4 V			14-SOIC	18 V	3 V	NOR Gate	11 V	3.5 V	-55 °C	125 °C	0.154 in	3.9 mm

Catalog

Military 4-ch, 2-input, 3-V to 18-V NOR gates

Key Features

• Propagation delay time = 60 ns (typ.) at CL= 50 pF, VDD= 10 VBuffered inputs and outputsStandardized symmetrical output characteristics100% tested for maximum quiescent current at 20 V5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (over full package temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Data sheet acquired from Harris SemiconductorPropagation delay time = 60 ns (typ.) at CL= 50 pF, VDD= 10 VBuffered inputs and outputsStandardized symmetrical output characteristics100% tested for maximum quiescent current at 20 V5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (over full package temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Data sheet acquired from Harris Semiconductor

Description

CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes). CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).