ADCLK944 Series

2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

Catalog

2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

Part	Input	Number of Circuits	Frequency - Max [Max]	Type	Output	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Ratio - Input:Output	Contents	Utilized IC / Part	Supplied Contents	Function	Secondary Attributes	Primary Attributes
Analog Devices ADCLK944BCPZ-WP	CML CMOS LVDS LVPECL	1	7 GHz	Fanout Buffer (Distribution)	ECL LVPECL	16-WFQFN Exposed Pad CSP	85 °C	-40 °C	Surface Mount	3.63 V	2.375 V	16-LFCSP-WQ (3x3)	1:4
Analog Devices ADCLK944/PCBZ				Timing										Board(s)	ADCLK944	Board(s)	Clock Buffer	Differential Output	Differential Inputs
Analog Devices ADCLK944BCPZ-R7	CML CMOS LVDS LVPECL	1	7 GHz	Fanout Buffer (Distribution)	ECL LVPECL	16-WFQFN Exposed Pad CSP	85 °C	-40 °C	Surface Mount	3.63 V	2.375 V	16-LFCSP-WQ (3x3)	1:4
Analog Devices ADCLK944BCPZ-R2	CML CMOS LVDS LVPECL	1	7 GHz	Fanout Buffer (Distribution)	ECL LVPECL	16-WFQFN Exposed Pad CSP	85 °C	-40 °C	Surface Mount	3.63 V	2.375 V	16-LFCSP-WQ (3x3)	1:4

Catalog

2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

Key Features

• Operating frequency: 7.0 GHz

• Broadband random jitter: 50 fs rms

• On-chip input terminations

• Power supply (VCC− VEE): 2.5 V to 3.3 V

Description

The ADCLK944 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFpin is available for biasing ac-coupled inputs.The ADCLK944 features four full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCCto the positive supply and VEEto ground. For ECL operation, bias VCCto ground and VEEto the negative supply.The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC− 2 V for a total differential output swing of 1.6 V.The ADCLK944 is available in a 16-lead LFCSP and is specified for operation over the standard industrial temperature range of −40°C to +85°C.APPLICATIONSLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation