Catalog
Low jitter, dual 1:4 universal-to-LVPECL buffer
Key Features
• Dual 1:4 Differential BufferTwo Clock InputsUniversal Inputs Can Accept LVPECL,LVDS, LVCMOS/LVTTLEight LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 78 mAVery Low Additive Jitter: <100 fs,RMS in 10-kHz to 20-MHz Offset Range2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 450 psMaximum 15 ps Within Bank Output SkewLVPECL Reference Voltage, VAC_REF,Available for Capacitive-Coupled InputsIndustrial Temperature Range: –40°C to +85°CSupports 105°C PCB Temperature (Measured with a Thermal Pad)Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) PackageESD Protection Exceeds 2000 V (HBM)Dual 1:4 Differential BufferTwo Clock InputsUniversal Inputs Can Accept LVPECL,LVDS, LVCMOS/LVTTLEight LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 78 mAVery Low Additive Jitter: <100 fs,RMS in 10-kHz to 20-MHz Offset Range2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 450 psMaximum 15 ps Within Bank Output SkewLVPECL Reference Voltage, VAC_REF,Available for Capacitive-Coupled InputsIndustrial Temperature Range: –40°C to +85°CSupports 105°C PCB Temperature (Measured with a Thermal Pad)Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) PackageESD Protection Exceeds 2000 V (HBM)
Description
AI
The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.
The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.
