Zenode.ai Logo
Beta
Texas Instruments-SN74AHCT125N Buffers and Line Drivers SN74AHCT125N_img1
Integrated Circuits (ICs)

SN74AHCT125N

Active
Texas Instruments

4-CH, 4.5-V TO 5.5-V BUFFERS WITH TTL-COMPATIBLE CMOS INPUTS AND 3-STATE OUTPUTS

Deep-Dive with AI

Search across all available documentation for this part.

Texas Instruments-SN74AHCT125N Buffers and Line Drivers SN74AHCT125N_img1
Integrated Circuits (ICs)

SN74AHCT125N

Active
Texas Instruments

4-CH, 4.5-V TO 5.5-V BUFFERS WITH TTL-COMPATIBLE CMOS INPUTS AND 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74AHCT125N
Current - Output High, Low [custom]8 mA
Current - Output High, Low [custom]8 mA
Logic TypeBuffer, Non-Inverting
Mounting TypeThrough Hole
Number of Bits per Element1
Number of Elements4
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case14-DIP
Package / Case [x]0.3 "
Package / Case [y]7.62 mm
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

SN74AHCT125-EP Series

Enhanced product 4-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

PartNumber of Bits per ElementVoltage - Supply [Min]Voltage - Supply [Max]Operating Temperature [Max]Operating Temperature [Min]Current - Output High, Low [custom]Current - Output High, Low [custom]Package / CasePackage / Case [y]Package / Case [x]Mounting TypeOutput TypeLogic TypeNumber of ElementsSupplier Device PackagePackage / Case [custom]Package / Case [custom]QualificationGrade
Texas Instruments-SN74AHCT125N Buffers and Line Drivers SN74AHCT125N_img1
Texas Instruments
1
4.5 V
5.5 V
85 °C
-40 °C
8 mA
8 mA
14-DIP
7.62 mm
0.3 "
Through Hole
3-State
Buffer
Non-Inverting
4
14-SOIC
Texas Instruments
1
4.5 V
5.5 V
125 °C
-40 °C
8 mA
8 mA
14-SOIC
3.9 mm
0.154 in
Surface Mount
3-State
Buffer
Non-Inverting
4
14-TSSOP
Texas Instruments
1
4.5 V
5.5 V
85 °C
-40 °C
8 mA
8 mA
14-TSSOP
Surface Mount
3-State
Buffer
Non-Inverting
4
14-TSSOP
0.173 "
4.4 mm
14-TSSOP
Texas Instruments
1
4.5 V
5.5 V
125 °C
-40 °C
8 mA
8 mA
14-TSSOP
Surface Mount
3-State
Buffer
Non-Inverting
4
14-TSSOP
0.173 "
4.4 mm
AEC-Q100
Automotive
14-TSSOP
Texas Instruments
1
4.5 V
5.5 V
85 °C
-40 °C
8 mA
8 mA
14-TSSOP
Surface Mount
3-State
Buffer
Non-Inverting
4
14-TSSOP
0.173 "
4.4 mm
14-SOIC
Texas Instruments
1
4.5 V
5.5 V
85 °C
-40 °C
8 mA
8 mA
14-SOIC
3.9 mm
0.154 in
Surface Mount
3-State
Buffer
Non-Inverting
4
TSSOP (PW)
Texas Instruments
1
4.5 V
5.5 V
125 °C
-40 °C
8 mA
8 mA
14-TSSOP
Surface Mount
3-State
Buffer
Non-Inverting
4
14-TSSOP
0.173 "
4.4 mm
14-SOIC
Texas Instruments
1
4.5 V
5.5 V
85 °C
-40 °C
8 mA
8 mA
14-SOIC
3.9 mm
0.154 in
Surface Mount
3-State
Buffer
Non-Inverting
4
SOIC (D)
Texas Instruments
1
4.5 V
5.5 V
125 °C
-40 °C
8 mA
8 mA
14-SOIC
3.9 mm
0.154 in
Surface Mount
3-State
Buffer
Non-Inverting
4
Texas Instruments-SN74HC32NSRG4 Logic Gates OR Gate 4-Element 2-IN CMOS 14-Pin SOP T/R
Texas Instruments
1
4.5 V
5.5 V
85 °C
-40 °C
8 mA
8 mA
14-SOIC
5.3 mm
0.209 "
Surface Mount
3-State
Buffer
Non-Inverting
4
14-SO

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 5$ 0.61
10$ 0.43
50$ 0.39
100$ 0.34
200$ 0.34
DigikeyTube 1$ 0.72
10$ 0.63
25$ 0.59
100$ 0.48
250$ 0.45
500$ 0.38
1000$ 0.31
2500$ 0.28
5000$ 0.26
Texas InstrumentsTUBE 1$ 0.60
100$ 0.41
250$ 0.32
1000$ 0.21

Description

General part information

SN74AHCT125-EP Series

The SN74AHCT125-Q1 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AHCT125-Q1 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable ( OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.