
SY100EL33LZG
ActiveMULTIPLIER/DIVIDER, DIVIDE BY 4, 1 INPUT, 4.2 GHZ, 3 V TO 3.8 V, 8 PINS, SOIC
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SY100EL33LZG
ActiveMULTIPLIER/DIVIDER, DIVIDE BY 4, 1 INPUT, 4.2 GHZ, 3 V TO 3.8 V, 8 PINS, SOIC
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Technical Specifications
Parameters and characteristics for this part
| Specification | SY100EL33LZG |
|---|---|
| Count Rate | 4.2 GHz |
| Logic Type | Divide-by-4 |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 2 bits |
| Number of Elements | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Package Length | 0.154 in |
| Package Name | 8-SOIC |
| Package Width | 3.9 mm |
| Reset | Asynchronous |
| Trigger Type | Positive, Negative |
| Voltage - Supply (Maximum) | 5 V |
| Voltage - Supply (Minimum) | 3.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | Updated |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 2.05 | <2d |
| 25 | $ 1.71 | |||
| 100 | $ 1.65 | |||
CAD
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Description
General part information
100EL33 Series
The SY100EL33/L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL33/L only; the VBB output has limited current sink and source capability. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset input allows for the synchronization of multiple EL33/Ls in a system.3.3V and 5V power supply options 650ps propagation delay 4.0GHz toggle frequency High bandwidth output transistions Internal 75k? input pull-down resistors Available in 8-pin SOIC package
Documents
Technical documentation and resources