Zenode.ai Logo
Beta
56-TSSOP
Integrated Circuits (ICs)

SN74ABT16823DGGR

Active
Texas Instruments

18-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

Deep-Dive with AI

Search across all available documentation for this part.

56-TSSOP
Integrated Circuits (ICs)

SN74ABT16823DGGR

Active
Texas Instruments

18-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ABT16823DGGR
Clock Frequency150 MHz
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Current - Quiescent (Iq)0.5 mA
Input Capacitance3.5 pF
Max Propagation Delay @ V, Max CL5.5 ns
Mounting TypeSurface Mount
Number of Bits per Element9
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State, Non-Inverted
Package / Case6.1 mm
Package / Case0.24 in
Package / Case56-TFSOP
Supplier Device Package56-TSSOP
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 3.06
Digi-Reel® 1$ 3.06
Tape & Reel (TR) 2000$ 1.53
6000$ 1.48
Texas InstrumentsLARGE T&R 1$ 2.31
100$ 2.02
250$ 1.42
1000$ 1.14

Description

General part information

SN74ABT16823 Series

These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The 'ABT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable () input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Takinghigh disables the clock buffer, latching the outputs. Taking the clear () input low causes the Q outputs to go low independently of the clock.

A buffered output-enable () input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.