Specification	SN74ABT16823DLR

Clock Frequency	150 MHz
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Current - Quiescent (Iq)	0.5 mA
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	5.5 ns
Mounting Type	Surface Mount
Number of Bits per Element	9
Number of Elements	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Non-Inverted
Package / Case	0.295 in
Package / Case	56-BSSOP
Package / Case	7.5 mm
Supplier Device Package	56-SSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ABT16823 Series

18-Bit Bus Interface Flip-Flops With 3-State Outputs

Part	Input Capacitance	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Clock Frequency	Supplier Device Package	Package / Case	Package / Case	Package / Case	Type	Max Propagation Delay @ V, Max CL	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Bits per Element	Trigger Type	Mounting Type	Current - Quiescent (Iq)	Operating Temperature [Max]	Operating Temperature [Min]	Number of Elements	Package / Case	Package / Case [y]
Texas Instruments SN74ABT16823DL	3.5 pF	64 mA	32 mA	Non-Inverted Tri-State	150 MHz	56-SSOP	0.295 in	56-BSSOP	7.5 mm	D-Type	5.5 ns	4.5 V	5.5 V	9	Positive Edge	Surface Mount	0.5 mA	85 °C	-40 °C	2
Texas Instruments SN74ABT16823DLG4	3.5 pF	64 mA	32 mA	Non-Inverted Tri-State	150 MHz	56-SSOP	0.295 in	56-BSSOP	7.5 mm	D-Type	5.5 ns	4.5 V	5.5 V	9	Positive Edge	Surface Mount	0.5 mA	85 °C	-40 °C	2
Texas Instruments SN74ABT16823DGVR	3.5 pF	64 mA	32 mA	Non-Inverted Tri-State	150 MHz	56-TVSOP		56-TFSOP		D-Type	5.5 ns	4.5 V	5.5 V	9	Positive Edge	Surface Mount	0.5 mA	85 °C	-40 °C	2	0.173 in	4.4 mm
Texas Instruments SN74ABT16823DGGR	3.5 pF	64 mA	32 mA	Non-Inverted Tri-State	150 MHz	56-TSSOP	0.24 in	56-TFSOP	6.1 mm	D-Type	5.5 ns	4.5 V	5.5 V	9	Positive Edge	Surface Mount	0.5 mA	85 °C	-40 °C	2
Texas Instruments SN74ABT16823DLR	3.5 pF	64 mA	32 mA	Non-Inverted Tri-State	150 MHz	56-SSOP	0.295 in	56-BSSOP	7.5 mm	D-Type	5.5 ns	4.5 V	5.5 V	9	Positive Edge	Surface Mount	0.5 mA	85 °C	-40 °C	2

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 3.36
	Digi-Reel®	1	$ 3.36
	Tape & Reel (TR)	1000	$ 1.78
		2000	$ 1.69
		5000	$ 1.62
Texas Instruments	LARGE T&R	1	$ 2.54
		100	$ 2.22
		250	$ 1.56
		1000	$ 1.26

Description

General part information

SN74ABT16823 Series

These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The 'ABT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable () input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Takinghigh disables the clock buffer, latching the outputs. Taking the clear () input low causes the Q outputs to go low independently of the clock.

A buffered output-enable () input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

Documents

Technical documentation and resources

SN74ABT16823DLR

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SN74ABT16823DLR

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Technical Specifications

SN74ABT16823 Series

Pricing

Description

SN74ABT16823 Series

Documents

Selecting the Right Level Translation Solution (Rev. A)

Designing With Logic (Rev. C)

Logic Guide (Rev. AB)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)

LOGIC Pocket Data Book (Rev. B)

Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)

Power-Up Behavior of Clocked Devices (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Advanced Bus Interface Logic Selection Guide

Quad Flatpack No-Lead Logic Packages (Rev. D)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Input and Output Characteristics of Digital Integrated Circuits

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

TI IBIS File Creation, Validation, and Distribution Processes

Understanding Advanced Bus-Interface Products Design Guide

Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)

Live Insertion

18-Bit Bus-Interface Flip-Flops With 3-State Outputs datasheet (Rev. C)

SN74ABT16823 Series