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121-TFBGA
Integrated Circuits (ICs)

MCP37D11-200E/TE

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Microchip Technology

12-BIT, 200 MSPS, PIPELINED ADC WITH 8-CHANNEL MUX WITH DDC 121 SIP 8X8X1.08MM TRAY ROHS COMPLIANT: YES

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121-TFBGA
Integrated Circuits (ICs)

MCP37D11-200E/TE

Active
Microchip Technology

12-BIT, 200 MSPS, PIPELINED ADC WITH 8-CHANNEL MUX WITH DDC 121 SIP 8X8X1.08MM TRAY ROHS COMPLIANT: YES

Technical Specifications

Parameters and characteristics for this part

SpecificationMCP37D11-200E/TE
ArchitecturePipelined
ConfigurationMUX-S/H-ADC
Data InterfaceLVDS - Parallel, Parallel
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters1
Number of Bits12 bits
Number of Inputs8, 1, 2, 4
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case121-TFBGA
Ratio - S/H:ADC1:1
Reference TypeInternal
Sampling Rate (Per Second)200 M
Supplier Device Package121-TFBGA (8x8)
Voltage - Supply, Analog [Max]1.89 V
Voltage - Supply, Analog [Min]1.14 V
Voltage - Supply, Digital [Max]1.89 V
Voltage - Supply, Digital [Min]1.14 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Microchip DirectTRAY 1$ 30.86
25$ 25.71
100$ 23.38
1000$ 21.60
5000$ 20.48
NewarkEach 100$ 23.38

Description

General part information

MCP37D11-200 Series

The MCP37D11-200 is a 12-bit pipelined A/D converter with a maximum sampling rate of 200 Msps. The high accuracy of 71.3 dB Signal-to-Noise Ratio (SNR) and over 90 dB Spurious Free Dynamic Range (SFDR) enable high precision measurements of fast input signals. The device operates at very low power consumption of 468 mW at 200 Msps including LVDS digital I/O. Lower power saving modes are available at 144 mW for Standby and 28 mW for Shutdown. The MCP37D11-200 includes many digital processing features that simplify system design, cost and power usage. These include an integrated digital down-converter with onboard NCO, decimation filters for improved SNR, a noise-shaping requantizer for SNR improvement around a bandwidth of interest, individual phase, offset and gain adjustment and a fractional delay recovery for time-delay corrections in multi-channel modes. Data is available through the serial DDR LVDS or parallel CMOS interface and configured via SPI. The device is available in the TFBGA-121 and VTLA-124 packages. TFBGA-121 package is qualified for automotive applications (AEC-Q100).