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Integrated Circuits (ICs)

SN74AHC138NSR

Active
Texas Instruments

2V-TO-5.5V 3-LINE TO 8-LINE DECODER AND DEMULTIPLEXER

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16 SO
Integrated Circuits (ICs)

SN74AHC138NSR

Active
Texas Instruments

2V-TO-5.5V 3-LINE TO 8-LINE DECODER AND DEMULTIPLEXER

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74AHC138NSR
Circuit1 x 3:8
Current - Output High, Low [custom]8 mA
Current - Output High, Low [custom]8 mA
Independent Circuits1
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case0.209 "
Package / Case16-SOIC
Package / Case5.3 mm
Supplier Device Package16-SO
TypeDecoder/Demultiplexer
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2 V
Voltage Supply SourceSingle Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.70
10$ 0.62
25$ 0.58
100$ 0.48
250$ 0.44
500$ 0.38
1000$ 0.30
Digi-Reel® 1$ 0.70
10$ 0.62
25$ 0.58
100$ 0.48
250$ 0.44
500$ 0.38
1000$ 0.30
Tape & Reel (TR) 2000$ 0.27
6000$ 0.25
10000$ 0.24
Texas InstrumentsLARGE T&R 1$ 0.58
100$ 0.39
250$ 0.30
1000$ 0.20

Description

General part information

SN74AHC138 Series

The SNx4AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SNx4AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.