
SN74AHC138D
Obsolete2V-TO-5.5V 3-LINE TO 8-LINE DECODER AND DEMULTIPLEXER
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SN74AHC138D
Obsolete2V-TO-5.5V 3-LINE TO 8-LINE DECODER AND DEMULTIPLEXER
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHC138D |
|---|---|
| Circuit | 1 x 3:8 |
| Current - Output High, Low [custom] | 8 mA |
| Current - Output High, Low [custom] | 8 mA |
| Independent Circuits | 1 |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 16-SOIC |
| Type | Decoder/Demultiplexer |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
| Voltage Supply Source | Single Supply |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 1.82 | |
| 10 | $ 1.15 | |||
| 25 | $ 0.98 | |||
| Texas Instruments | TUBE | 1 | $ 0.86 | |
| 100 | $ 0.66 | |||
| 250 | $ 0.49 | |||
| 1000 | $ 0.35 | |||
Description
General part information
SN74AHC138 Series
The SNx4AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The SNx4AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
Documents
Technical documentation and resources