Specification	SN74ALS533ADW

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low [custom]	24 mA
Current - Output High, Low [custom]	2.6 mA
Delay Time - Propagation	6 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output Type	Tri-State
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ALS533A Series

Octal D-Type Transparent Latches With 3-State Outputs

Part	Package / Case	Package / Case [y]	Package / Case [y]	Delay Time - Propagation	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Circuit [custom]	Circuit [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Independent Circuits	Output Type	Logic Type	Mounting Type	Supplier Device Package
Texas Instruments SN74ALS533ADWR	20-SOIC	0.295 in	7.5 mm	6 ns	24 mA	2.6 mA	4.5 V	5.5 V	8	8	70 °C	0 °C	1	Tri-State	D-Type Transparent Latch	Surface Mount	20-SOIC
Texas Instruments SN74ALS533ADW	20-SOIC	0.295 in	7.5 mm	6 ns	24 mA	2.6 mA	4.5 V	5.5 V	8	8	70 °C	0 °C	1	Tri-State	D-Type Transparent Latch	Surface Mount	20-SOIC

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 4.65
		10	$ 4.18
		25	$ 3.95
		100	$ 3.42
		250	$ 3.25
		500	$ 2.92
		1000	$ 2.46
		2500	$ 2.34
Texas Instruments	TUBE	1	$ 3.68
		100	$ 3.00
		250	$ 2.36
		1000	$ 2.00

Description

General part information

SN74ALS533A Series

These 8-bit D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverses of the levels set up at the D inputs. The SN74ALS533A and SN74AS533A are functionally equivalent to the SN74ALS373A and SN74AS373, except for having inverted outputs.

A buffered output-enable () input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

Documents

Technical documentation and resources

Octal D-Type Transparent Latches With 3-State Outputs datasheet

Data sheet