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144-FCBGA
Integrated Circuits (ICs)

ADC12SJ1600AAVT

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Texas Instruments

SINGLE-CHANNEL, 12-BIT, 1.6-GSPS ADC WITH JESD204C INTERFACE AND INTEGRATED SAMPLE CLOCK GENERATOR

144-FCBGA
Integrated Circuits (ICs)

ADC12SJ1600AAVT

Active
Texas Instruments

SINGLE-CHANNEL, 12-BIT, 1.6-GSPS ADC WITH JESD204C INTERFACE AND INTEGRATED SAMPLE CLOCK GENERATOR

Technical Specifications

Parameters and characteristics for this part

SpecificationADC12SJ1600AAVT
ArchitecturePipelined, SAR
ConfigurationADC
Data InterfaceJESD204B/C
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters1
Number of Bits12 bits
Number of Inputs1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / CaseFCBGA, 144-FBGA
Ratio - S/H:ADC0:1
Sampling Rate (Per Second)1.6 G
Supplier Device Package144-FCBGA (10x10)
Voltage - Supply, Analog [Max]2 V, 1.15 V
Voltage - Supply, Analog [Min]1.8 V, 1.05 V
Voltage - Supply, Digital [Max]1.15 V
Voltage - Supply, Digital [Min]1.05 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 250$ 188.75
Texas InstrumentsSMALL T&R 1$ 169.36
100$ 153.30
250$ 148.92
1000$ 146.00

Description

General part information

ADC12SJ1600-Q1 Series

ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.