ADC12SJ1600-Q1 Series

Single-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator

Catalog

Single-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator

Part	Data Interface	Number of Bits	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Supplier Device Package	Number of A/D Converters	Number of Inputs	Ratio - S/H:ADC	Architecture	Sampling Rate (Per Second)	Mounting Type	Configuration	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Package / Case	Input Type	Operating Temperature [Max]	Operating Temperature [Min]	Grade	Qualification	Reference Type	Features
Texas Instruments ADC12SJ1600AAV	JESD204B/C	12 bits	1.05 V 1.8 V	1.15 V 2 V	144-FCBGA (10x10)	1	1	0:1	Pipelined SAR	1.6 G	Surface Mount	ADC	1.15 V	1.05 V	144-FBGA FCBGA	Differential	85 °C	-40 °C
Texas Instruments ADC12SJ1600AAVTQ1	JESD204C SPI	12 bits	1.05 V 1.8 V	1.15 V 2 V	144-FCBGA (10x10)	4	1	0:4	Flash Pipelined SAR	1.6 G	Surface Mount	ADC	1.15 V	1.05 V	144-FBGA FCBGA	Differential Single Ended	125 °C	-40 °C	Automotive	AEC-Q100	External Internal	Temperature Sensor
Texas Instruments ADC12SJ1600AAVT	JESD204B/C	12 bits	1.05 V 1.8 V	1.15 V 2 V	144-FCBGA (10x10)	1	1	0:1	Pipelined SAR	1.6 G	Surface Mount	ADC	1.15 V	1.05 V	144-FBGA FCBGA	Differential	85 °C	-40 °C
Texas Instruments ADC12SJ1600AAVQ1	SPI	12 bits	1.05 V 1.8 V	1.15 V 2 V	144-FCBGA (10x10)	4	1	0:4	Flash Pipelined SAR	1.6 G	Surface Mount	ADC	1.15 V	1.05 V	144-FBGA FCBGA	Differential Single Ended	125 °C	-40 °C	Automotive	AEC-Q100	External Internal	Temperature Sensor

Catalog

Single-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator

Key Features

• AEC-Q100 qualified for automotive applications:Temperature grade 1: –40°C to +125°C, TAADC Core:Resolution: 12 BitMaximum sampling rate: 1.6GSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1dBFS):SNR (100MHz): 57.4dBFSENOB (100MHz): 9.1 BitsSFDR (100MHz): 64dBcNoise floor (–20dBFS): –147dBFSFull-scale input voltage: 800mVPP-DIFFFull-power input bandwidth: 6GHzJESD204C Serial data interface:Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (1GSPS):Quad Channel: 477mW / channelDual channel: 700mW / channelSingle channel: 1000mWPower supplies: 1.1V, 1.9VAEC-Q100 qualified for automotive applications:Temperature grade 1: –40°C to +125°C, TAADC Core:Resolution: 12 BitMaximum sampling rate: 1.6GSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1dBFS):SNR (100MHz): 57.4dBFSENOB (100MHz): 9.1 BitsSFDR (100MHz): 64dBcNoise floor (–20dBFS): –147dBFSFull-scale input voltage: 800mVPP-DIFFFull-power input bandwidth: 6GHzJESD204C Serial data interface:Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2–8.2GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (1GSPS):Quad Channel: 477mW / channelDual channel: 700mW / channelSingle channel: 1000mWPower supplies: 1.1V, 1.9V

Description

ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications. Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications. Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.