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TSSOP (PW)
Integrated Circuits (ICs)

TPIC6C596PWRG4

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Texas Instruments

IC PWR 8-BIT SHIFT REGIS 16TSSOP

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TSSOP (PW)
Integrated Circuits (ICs)

TPIC6C596PWRG4

Active
Texas Instruments

IC PWR 8-BIT SHIFT REGIS 16TSSOP

Technical Specifications

Parameters and characteristics for this part

SpecificationTPIC6C596PWRG4
FunctionSerial to Parallel, Serial
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeOpen Drain
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package16-TSSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.34
10$ 1.20
25$ 1.14
100$ 0.94
250$ 0.88
500$ 0.77
Digi-Reel® 1$ 1.34
10$ 1.20
25$ 1.14
100$ 0.94
250$ 0.88
500$ 0.77
Tape & Reel (TR) 2000$ 0.57
6000$ 0.54
10000$ 0.52
Texas InstrumentsLARGE T&R 1$ 1.12
100$ 0.86
250$ 0.64
1000$ 0.46

Description

General part information

TPIC6C596 Series

The TPIC6C596 device is a monolithic, medium-voltage, low-current, 8-bit shift register designed for use in systems that require relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other low-current or medium-voltage loads.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high. WhenCLRis low, all registers in the device are cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. WhenGis held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability.

The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference.