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Integrated Circuits (ICs)

TPIC6C596DRG4

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Texas Instruments

SHIFT REGISTER SINGLE 8-BIT SERIAL TO SERIAL/PARALLEL 16-PIN SOIC T/R

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SOIC (D)
Integrated Circuits (ICs)

TPIC6C596DRG4

Active
Texas Instruments

SHIFT REGISTER SINGLE 8-BIT SERIAL TO SERIAL/PARALLEL 16-PIN SOIC T/R

Technical Specifications

Parameters and characteristics for this part

SpecificationTPIC6C596DRG4
FunctionSerial to Parallel, Serial
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeOpen Drain
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Supplier Device Package16-SOIC
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

TPIC6C596 Series

Automotive 8-bit shift register

PartMounting TypeOutput TypePackage / CasePackage / CasePackage / CaseOperating Temperature [Max]Operating Temperature [Min]Supplier Device PackageFunctionNumber of Bits per ElementLogic TypeNumber of ElementsVoltage - Supply [Min]Voltage - Supply [Max]Package / Case [x]Package / Case [y]QualificationGrade
PDIP (N)
Texas Instruments
Through Hole
Open Drain
0.3 in
16-DIP
7.62 mm
125 °C
-40 °C
16-PDIP
Serial to Parallel
Serial
8
Shift Register
1
4.5 V
5.5 V
SOIC (D)
Texas Instruments
Surface Mount
Open Drain
16-SOIC
125 °C
-40 °C
16-SOIC
Serial to Parallel
Serial
8
Shift Register
1
4.5 V
5.5 V
0.154 in
3.9 mm
SOIC (D)
Texas Instruments
Surface Mount
Open Drain
16-SOIC
125 °C
-40 °C
16-SOIC
Serial to Parallel
Serial
8
Shift Register
1
4.5 V
5.5 V
0.154 in
3.9 mm
Texas Instruments-LM5026MT/NOPB PWM and Resonant Controllers Current Mode PWM Controller 3A 590kHz 16-Pin TSSOP Tube
Texas Instruments
Surface Mount
Open Drain
16-TSSOP
125 °C
-40 °C
16-TSSOP
Serial to Parallel
Serial
8
Shift Register
1
4.5 V
5.5 V
0.173 in
4.4 mm
TSSOP (PW)
Texas Instruments
Surface Mount
Open Drain
16-TSSOP
125 °C
-40 °C
16-TSSOP
Serial to Parallel
Serial
8
Shift Register
1
4.5 V
5.5 V
0.173 in
4.4 mm
SOIC (D)
Texas Instruments
Surface Mount
Open Drain
16-SOIC
125 °C
-40 °C
16-SOIC
Serial to Parallel
Serial
8
Shift Register
1
4.5 V
5.5 V
0.154 in
3.9 mm
16 SOIC
Texas Instruments
Surface Mount
Open Drain
16-SOIC
125 °C
-40 °C
16-SOIC
Serial to Parallel
Serial
8
Shift Register
1
4.5 V
5.5 V
0.154 in
3.9 mm
16 SOIC
Texas Instruments
Surface Mount
Open Drain
16-SOIC
125 °C
-40 °C
16-SOIC
Serial to Parallel
Serial
8
Shift Register
1
4.5 V
5.5 V
0.154 in
3.9 mm
AEC-Q100
Automotive

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.52
Digi-Reel® 1$ 1.52
Tape & Reel (TR) 2500$ 0.64
5000$ 0.61
12500$ 0.59
Texas InstrumentsLARGE T&R 1$ 1.12
100$ 0.86
250$ 0.64
1000$ 0.46

Description

General part information

TPIC6C596 Series

The TPIC6C596 device is a monolithic, medium-voltage, low-current, 8-bit shift register designed for use in systems that require relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other low-current or medium-voltage loads.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high. WhenCLRis low, all registers in the device are cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. WhenGis held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability.

The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference.