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Technical Specifications
Parameters and characteristics for this part
| Specification | CY29FCT520ATSOC |
|---|---|
| Function | Universal |
| Logic Type | Register, Pipeline |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 24-SOIC |
| Package / Case [custom] | 7.5 mm |
| Package / Case [custom] | 0.295 in |
| Supplier Device Package | 24-SOIC |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 150 | $ 6.48 | |
| Texas Instruments | TUBE | 1 | $ 6.63 | |
| 100 | $ 5.41 | |||
| 250 | $ 4.25 | |||
| 1000 | $ 3.60 | |||
Description
General part information
CY29FCT520T Series
The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0and S1).
The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.
In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.
Documents
Technical documentation and resources
