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74ALVC162244T
Integrated Circuits (ICs)

74VCX16244MTDX

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ON Semiconductor

LOW-VOLTAGE 1.8/2.5/3.3 V 16-BIT BUFFER WITH 3.6 V-TOLERANT INPUTS AND OUTPUTS (3-STATE, NON-INVERTING)

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74ALVC162244T
Integrated Circuits (ICs)

74VCX16244MTDX

Active
ON Semiconductor

LOW-VOLTAGE 1.8/2.5/3.3 V 16-BIT BUFFER WITH 3.6 V-TOLERANT INPUTS AND OUTPUTS (3-STATE, NON-INVERTING)

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Technical Specifications

Parameters and characteristics for this part

Specification74VCX16244MTDX
Current - Output High, Low24 mA
Logic TypeBuffer, Non-Inverting
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements4
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case48-TFSOP
Package / Case0.24 in
Package / Case [custom]6.1 mm
Supplier Device Package48-TSSOP
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]1.2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBulk 333$ 0.90
TMEN/A 1$ 0.87
5$ 0.79
25$ 0.70
100$ 0.65
250$ 0.59

Description

General part information

74VCX162244 Series

The 74VCX16373 is an advanced performance, non-inverting 16-bit transparent latch. It is designed for very high-speed, very low-power operation in 1.8V, 2.5V or 3.3V systems. The VCX16373 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16-bit operation.When operating at 2.5V (or 1.8V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3V busses. It is guaranteed to be over-voltage tolerant to 3.6V.The 74VCX16373 contains 16 D-type latches with 3-state 3.6V-tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, (a latch output will change state each time its D input changes). When LE is LOW, the latch stores the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state outputs are controlled by the Output Enable (OEn)bar inputs. When OEbar is LOW, the outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.

Documents

Technical documentation and resources