CD74HC40103QM96EP
ActiveENHANCED PRODUCT HIGH SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTERS
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CD74HC40103QM96EP
ActiveENHANCED PRODUCT HIGH SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTERS
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC40103QM96EP |
|---|---|
| Count Rate | 18 MHz |
| Direction | Down |
| Logic Type | Binary Counter |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Reset | Asynchronous |
| Supplier Device Package | 16-SOIC |
| Timing | Synchronous |
| Trigger Type | Positive Edge |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 3.44 | |
| Digi-Reel® | 1 | $ 3.44 | ||
| Tape & Reel (TR) | 2500 | $ 1.73 | ||
| 5000 | $ 1.66 | |||
| Texas Instruments | LARGE T&R | 1 | $ 2.99 | |
| 100 | $ 2.62 | |||
| 250 | $ 1.84 | |||
| 1000 | $ 1.48 | |||
Description
General part information
CD74HC40103-EP Series
The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage synchronous down counter with a single output, which is active when the internal count is zero. The device contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count (TC)\ output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the clock (CP) output. Counting is inhibited when the terminal enable (TE)\ input is high. TC\ goes low when the count reaches zero, if TE\ is low, and remains low for one full clock period.
When the synchronous preset enable (PE)\ input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition, regardless of the state of TE\. When the asynchronous preset enable (PL)\ input is low, data at the P0-P7 inputs asynchronously are forced into the counter, regardless of the state of the PE\, TE\, or CP inputs. Inputs P0-P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset (MR)\ input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.
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Technical documentation and resources
