TheAD4030-24/AD4032-24 are 2 MSPS or 500 kSPS successive approximation register (SAR), analog-to-digital converters (ADC) with Easy Drive™. With a guaranteed maximum ±0.9 ppm integral nonlinearity (INL) and no missing codes at 24-bits, the AD4030-24/AD4032-24 achieve unparalleled precision from −40°C to +125°C. Figure 1 shows the functional architecture of the AD4030-24/AD4032-24.A low drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4030-24/AD4032-24 offer a typical dynamic range of 109 dB when using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 155.5 dB. The wide differential input and common mode ranges allow inputs to use the full ±VREFrange without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4030-24/AD4032-24. Both single-ended and differential signals are supported.The versatile Flexi-SPI serial peripheral interface (SPI) eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS or 500 kSPS. Echo clock mode and ADC host clock mode relax the timing requirements and simplify the use of digital isolators.The 7 mm × 7 mm, 64-Ball CSP_BGA package of the AD4030-24/AD4032-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout.APPLICATIONSAutomatic test equipmentDigital control loopsMedical instrumentationSeismologySemiconductor manufacturingScientific instrumentation