Specification	SN74AHCT373DWR

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low [custom]	8 mA
Current - Output High, Low [custom]	8 mA
Delay Time - Propagation	1 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74AHCT373 Series

Octal Transparent D-Type Latches With 3-State Outputs

Part	Mounting Type	Delay Time - Propagation	Circuit [custom]	Circuit [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Independent Circuits	Voltage - Supply [Min]	Voltage - Supply [Max]	Logic Type	Supplier Device Package	Output Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case	Package / Case [y]	Package / Case [x]	Package / Case	Package / Case	Package / Case [y]
Texas Instruments SN74AHCT373DBRG4	Surface Mount	1 ns	8	8	85 °C	-40 °C	1	4.5 V	5.5 V	D-Type Transparent Latch	20-SSOP	Tri-State	8 mA	8 mA	20-SSOP
Texas Instruments SN74AHCT373PW	Surface Mount	1 ns	8	8	85 °C	-40 °C	1	4.5 V	5.5 V	D-Type Transparent Latch	20-TSSOP	Tri-State	8 mA	8 mA	20-TSSOP	4.4 mm	0.173 in
Texas Instruments SN74AHCT373PWR	Surface Mount	1 ns	8	8	85 °C	-40 °C	1	4.5 V	5.5 V	D-Type Transparent Latch	20-TSSOP	Tri-State	8 mA	8 mA	20-TSSOP	4.4 mm	0.173 in
Texas Instruments SN74AHCT373NSR	Surface Mount	1 ns	8	8	85 °C	-40 °C	1	4.5 V	5.5 V	D-Type Transparent Latch	20-SO	Tri-State	8 mA	8 mA	20-SOIC			0.209 "	5.3 mm
Texas Instruments SN74AHCT373N	Through Hole	1 ns	8	8	85 °C	-40 °C	1	4.5 V	5.5 V	D-Type Transparent Latch	20-PDIP	Tri-State	8 mA	8 mA	20-DIP			0.3 in	7.62 mm
Texas Instruments SN74AHCT373PWRG4	Surface Mount	1 ns	8	8	85 °C	-40 °C	1	4.5 V	5.5 V	D-Type Transparent Latch	20-TSSOP	Tri-State	8 mA	8 mA	20-TSSOP	4.4 mm	0.173 in
Texas Instruments SN74AHCT373DBR	Surface Mount	1 ns	8	8	85 °C	-40 °C	1	4.5 V	5.5 V	D-Type Transparent Latch	20-SSOP	Tri-State	8 mA	8 mA	20-SSOP
Texas Instruments SN74AHCT373DWR	Surface Mount	1 ns	8	8	85 °C	-40 °C	1	4.5 V	5.5 V	D-Type Transparent Latch	20-SOIC	Tri-State	8 mA	8 mA	20-SOIC	0.295 in				7.5 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Arrow	N/A	2000	$ 0.15
Digikey	Cut Tape (CT)	1	$ 0.56
		10	$ 0.48
		25	$ 0.45
		100	$ 0.36
		250	$ 0.33
		500	$ 0.28
		1000	$ 0.22
	Digi-Reel®	1	$ 0.56
		10	$ 0.48
		25	$ 0.45
		100	$ 0.36
		250	$ 0.33
		500	$ 0.28
		1000	$ 0.22
	Tape & Reel (TR)	2000	$ 0.16
Texas Instruments	LARGE T&R	1	$ 0.36
		100	$ 0.25
		250	$ 0.19
		1000	$ 0.13

Description

General part information

SN74AHCT373 Series

The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

Documents

Technical documentation and resources

Datasheet

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

SN74AHCT373DWR

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SN74AHCT373DWR

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Technical Specifications

SN74AHCT373 Series

Pricing

Description

SN74AHCT373 Series

Documents

Datasheet

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Power-Up Behavior of Clocked Devices (Rev. B)

Little Logic Guide 2018 (Rev. G)

Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)

Selecting the Right Level Translation Solution (Rev. A)

How to Select Little Logic (Rev. A)

Logic Guide (Rev. AB)

AHC/AHCT Designer's Guide February 2000 (Rev. D)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Texas Instruments Little Logic Application Report

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Live Insertion

LOGIC Pocket Data Book (Rev. B)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Design Summary for WCSP Little Logic (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

CMOS Power Consumption and CPD Calculation (Rev. B)

Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)

Implications of Slow or Floating CMOS Inputs (Rev. E)

SN74AHCT373 Series