SN74AHCT373PWR
ActiveOCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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SN74AHCT373PWR
ActiveOCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHCT373PWR |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low [custom] | 8 mA |
| Current - Output High, Low [custom] | 8 mA |
| Delay Time - Propagation | 1 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 20-TSSOP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.48 | |
| 10 | $ 0.41 | |||
| 25 | $ 0.38 | |||
| 100 | $ 0.30 | |||
| 250 | $ 0.28 | |||
| 500 | $ 0.24 | |||
| 1000 | $ 0.18 | |||
| Digi-Reel® | 1 | $ 0.48 | ||
| 10 | $ 0.41 | |||
| 25 | $ 0.38 | |||
| 100 | $ 0.30 | |||
| 250 | $ 0.28 | |||
| 500 | $ 0.24 | |||
| 1000 | $ 0.18 | |||
| Tape & Reel (TR) | 2000 | $ 0.17 | ||
| 6000 | $ 0.16 | |||
| 10000 | $ 0.15 | |||
| 50000 | $ 0.14 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.30 | |
| 100 | $ 0.20 | |||
| 250 | $ 0.16 | |||
| 1000 | $ 0.10 | |||
Description
General part information
SN74AHCT373 Series
The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
Documents
Technical documentation and resources
