SN74SSTEB32866ZWLR
Active1.5-V/1.8-V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
Deep-Dive with AI
Search across all available documentation for this part.
SN74SSTEB32866ZWLR
Active1.5-V/1.8-V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74SSTEB32866ZWLR |
|---|---|
| Mounting Type | Surface Mount |
| Number of Bits | 25 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 96-LFBGA |
| Supplier Device Package | 96-BGA |
| Supplier Device Package [x] | 13.5 |
| Supplier Device Package [y] | 5.5 |
| Supply Voltage [Max] | 1.575 V |
| Supply Voltage [Min] | 1.425 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 11.09 | |
| Digi-Reel® | 1 | $ 11.09 | ||
| Tape & Reel (TR) | 1000 | $ 7.02 | ||
| Texas Instruments | LARGE T&R | 1 | $ 9.62 | |
| 100 | $ 7.84 | |||
| 250 | $ 6.16 | |||
| 1000 | $ 5.23 | |||
Description
General part information
SN74SSTEB32866 Series
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meets SSTL_18 and SSTL_15 specifications (depending on Supply voltage level), except the open-drain error (QERR) output.
The SN74SSTEB32866 operates from a differential clock (CLK andCLK). Data are registered at the crossing of CLK going high and CLK going low.
Documents
Technical documentation and resources