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PQFP / 80
Integrated Circuits (ICs)

HV57708PG-G

Active
Microchip Technology

EL DRIVER, 64-SEGMENT, CMOS, PQFP80, 20 X 14 MM, 3.40 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MO-112BF-1B, QFP-80

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PQFP / 80
Integrated Circuits (ICs)

HV57708PG-G

Active
Microchip Technology

EL DRIVER, 64-SEGMENT, CMOS, PQFP80, 20 X 14 MM, 3.40 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MO-112BF-1B, QFP-80

Technical Specifications

Parameters and characteristics for this part

SpecificationHV57708PG-G
FunctionSerial to Parallel
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element16
Number of Elements4
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypePush-Pull
Package / Case80-BQFP
Supplier Device Package80-PQFP (14x20)
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 12.05
25$ 10.02
100$ 9.68
Microchip DirectTRAY 1$ 12.05
25$ 10.02
100$ 9.11
1000$ 8.82
5000$ 8.70

Description

General part information

HV57708 Series

The HV57708 is a low voltage serial to high voltage parallel converter with push-pull outputs. The device has been designed for use as a driver for EL displays. It can also be used in any application requiring multiple output high voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays.

The device has 4 parallel 16-bit registers, permitting data rates 4x the speed of one (they are clocked together). There are also 64 latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE input is high. The data in the latches is stored when the LE is low.