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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74F175NSR |
|---|---|
| Clock Frequency | 140 MHz |
| Current - Output High, Low [custom] | 1 mA |
| Current - Output High, Low [custom] | 20 mA |
| Current - Quiescent (Iq) | 34 mA |
| Max Propagation Delay @ V, Max CL | 8.5 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 4 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Complementary |
| Package / Case | 0.209 " |
| Package / Case | 16-SOIC |
| Package / Case | 5.3 mm |
| Supplier Device Package | 16-SO |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.79 | |
| 10 | $ 0.70 | |||
| 25 | $ 0.65 | |||
| 100 | $ 0.53 | |||
| 250 | $ 0.50 | |||
| 500 | $ 0.42 | |||
| 1000 | $ 0.34 | |||
| Digi-Reel® | 1 | $ 0.79 | ||
| 10 | $ 0.70 | |||
| 25 | $ 0.65 | |||
| 100 | $ 0.53 | |||
| 250 | $ 0.50 | |||
| 500 | $ 0.42 | |||
| 1000 | $ 0.34 | |||
| Tape & Reel (TR) | 2000 | $ 0.31 | ||
| 6000 | $ 0.28 | |||
| 10000 | $ 0.27 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.66 | |
| 100 | $ 0.45 | |||
| 250 | $ 0.35 | |||
| 1000 | $ 0.23 | |||
Description
General part information
SN74F175 Series
This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
Documents
Technical documentation and resources
