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SOIC (D)
Integrated Circuits (ICs)

LP2995M/NOPB

Active
Texas Instruments

DDR TERMINATION REGULATOR, 0 TO 125DEG C

SOIC (D)
Integrated Circuits (ICs)

LP2995M/NOPB

Active
Texas Instruments

DDR TERMINATION REGULATOR, 0 TO 125DEG C

Technical Specifications

Parameters and characteristics for this part

SpecificationLP2995M/NOPB
ApplicationsDDR Terminator
Current - Supply250 µA
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]0 °C
Package / Case8-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Supplier Device Package8-SOIC
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2.2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 2.36
10$ 1.51
25$ 1.29
100$ 1.04
250$ 0.92
500$ 0.85
1000$ 0.79
2500$ 0.72
5000$ 0.68
NewarkEach 1$ 2.13
10$ 1.98
25$ 1.84
50$ 1.76
190$ 1.65
285$ 1.57
570$ 1.55
Texas InstrumentsTUBE 1$ 1.23
100$ 0.95
250$ 0.70
1000$ 0.50

Description

General part information

LP2995 Series

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSEpin to provide superior load regulation and a VREFoutput as a reference for the chipset and DDR DIMMS.

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSEpin to provide superior load regulation and a VREFoutput as a reference for the chipset and DDR DIMMS.