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Technical Specifications
Parameters and characteristics for this part
| Specification | ISO721MDR |
|---|---|
| Channel Type | Unidirectional |
| Common Mode Transient Immunity (Min) [Min] | 25 kV/µs |
| Data Rate | 150 Mbps |
| Inputs - Side 1/Side 2 [custom] | 0 |
| Inputs - Side 1/Side 2 [custom] | 1 |
| Isolated Power | False |
| Mounting Type | Surface Mount |
| Number of Channels | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 8-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Propagation Delay tpLH / tpHL (Max) [Max] [custom] | 16 ns |
| Propagation Delay tpLH / tpHL (Max) [Max] [custom] | 16 ns |
| Pulse Width Distortion (Max) [Max] | 1 ns |
| Rise / Fall Time (Typ) [custom] | 1 ns |
| Rise / Fall Time (Typ) [custom] | 1 ns |
| Supplier Device Package | 8-SOIC |
| Technology | Capacitive Coupling |
| Type | General Purpose |
| Voltage - Isolation | 2500 Vrms |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 2500 | $ 1.58 | |
| Digikey | Cut Tape (CT) | 1 | $ 3.41 | |
| 10 | $ 3.06 | |||
| 25 | $ 2.90 | |||
| 100 | $ 2.51 | |||
| 250 | $ 2.38 | |||
| 500 | $ 2.14 | |||
| 1000 | $ 1.80 | |||
| Digi-Reel® | 1 | $ 3.41 | ||
| 10 | $ 3.06 | |||
| 25 | $ 2.90 | |||
| 100 | $ 2.51 | |||
| 250 | $ 2.38 | |||
| 500 | $ 2.14 | |||
| 1000 | $ 1.80 | |||
| Tape & Reel (TR) | 2500 | $ 1.71 | ||
| 5000 | $ 1.65 | |||
| Texas Instruments | LARGE T&R | 1 | $ 2.85 | |
| 100 | $ 2.36 | |||
| 250 | $ 1.69 | |||
| 1000 | $ 1.27 | |||
Description
General part information
ISO721M-EP Series
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching, and allows fast transient voltage changes between the input and output grounds without corrupting the output. The small capacitance and resulting time constant provide for fast operation with signaling rates(2)from 0 Mbps (dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.
Documents
Technical documentation and resources