Zenode.ai Logo
Beta
8-SOIC
Isolators

ISO721DRG4

Unknown
Texas Instruments

DGTL ISO 2500VRMS 1CH GP 8SOIC

Deep-Dive with AI

Search across all available documentation for this part.

8-SOIC
Isolators

ISO721DRG4

Unknown
Texas Instruments

DGTL ISO 2500VRMS 1CH GP 8SOIC

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationISO721DRG4
Channel TypeUnidirectional
Common Mode Transient Immunity (Min) [Min]25 kV/µs
Data Rate100 Mbps
Inputs - Side 1/Side 2 [custom]0
Inputs - Side 1/Side 2 [custom]1
Isolated PowerFalse
Mounting TypeSurface Mount
Number of Channels1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case8-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Propagation Delay tpLH / tpHL (Max) [custom]24 ns
Propagation Delay tpLH / tpHL (Max) [custom]24 ns
Pulse Width Distortion (Max) [Max]2 ns
Rise / Fall Time (Typ) [custom]1 ns
Rise / Fall Time (Typ) [custom]1 ns
Supplier Device Package8-SOIC
TechnologyCapacitive Coupling
TypeGeneral Purpose
Voltage - Isolation2500 Vrms
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 2500$ 2.38

Description

General part information

ISO721M-EP Series

The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground, and interfering with or damaging sensitive circuitry.

A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.

The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching, and allows fast transient voltage changes between the input and output grounds without corrupting the output. The small capacitance and resulting time constant provide for fast operation with signaling rates(2)from 0 Mbps (dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.

Documents

Technical documentation and resources

No documents available