M74HC280YRM13TR
ActiveREGISTERS 9 BIT PARITY GENERATOR 22NS 6V
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M74HC280YRM13TR
ActiveREGISTERS 9 BIT PARITY GENERATOR 22NS 6V
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | M74HC280YRM13TR |
|---|---|
| Current - Output High | 5.2 mA |
| Current - Output Low | 5.2 mA |
| Grade | Automotive |
| Logic Type | Parity Generator |
| Mounting Type | Surface Mount |
| Number of Circuits (Bit) | 9 Bit |
| Operating Temperature (Max) | 125 °C |
| Operating Temperature (Min) | -40 °C |
| Package Length | 0.154 in |
| Package Name | 14-SOIC, 14-SO |
| Package Width | 3.9 mm |
| Qualification | AEC-Q100 |
| Voltage - Supply (Maximum) | 6 V |
| Voltage - Supply (Minimum) | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | Updated |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.47 | <2d |
| 10 | $ 0.33 | |||
| 25 | $ 0.29 | |||
| 100 | $ 0.25 | |||
| 250 | $ 0.24 | |||
| 500 | $ 0.22 | |||
| 1000 | $ 0.22 | |||
| Tape & Reel (TR) | 2500 | $ 0.21 | <2d | |
| 5000 | $ 0.20 | |||
| 7500 | $ 0.20 | |||
| 12500 | $ 0.19 | |||
| 17500 | $ 0.19 | |||
| 25000 | $ 0.19 | |||
| Mouser | N/A | 1 | $ 0.61 | 1m+ |
| 10 | $ 0.43 | |||
| 25 | $ 0.39 | |||
| 100 | $ 0.34 | |||
| 250 | $ 0.30 | |||
| 1000 | $ 0.29 | |||
| 2500 | $ 0.25 | |||
| 10000 | $ 0.25 | |||
| 20000 | $ 0.25 | |||
| TME | N/A | 2500 | $ 0.18 | <1d |
CAD
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Description
General part information
74HC280 Series
The M74HC280 is a high-speed CMOS 9-bit parity generator fabricated with silicon gate C2MOS technology.
It is composed of nine data inputs (A to I) and odd/even parity outputs (ΣODD and ΣEVEN). The nine data inputs control the output conditions. When the number of high-level inputs is odd, ΣODD outputs are kept high and ΣEVEN outputs are kept low. Conversely, when the number of high-level outputs is even, ΣEVEN outputs are kept high and ΣODD outputs are kept low. The IC generates either odd or even parity making the application flexible. The word-length capability is easily expanded by cascading.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
Documents
Technical documentation and resources
