
ADN2817ACPZ-RL7
ActiveCONTINUOUS RATE 10 MBPS TO 2.7 GBPS CLOCK AND DATA RECOVERY IC (WITH HIGH SENSITIVITY LIMITING AMP)
Deep-Dive with AI
Search across all available documentation for this part.

ADN2817ACPZ-RL7
ActiveCONTINUOUS RATE 10 MBPS TO 2.7 GBPS CLOCK AND DATA RECOVERY IC (WITH HIGH SENSITIVITY LIMITING AMP)
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | ADN2817ACPZ-RL7 |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Input | CML |
| Main Purpose | SONET/SDH |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | CML |
| Package / Case | 32-WFQFN Exposed Pad, CSP |
| PLL | True |
| Ratio - Input:Output [custom] | 1:2 |
| Supplier Device Package | 32-LFCSP (5x5) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
ADN2817 Series
The ADN2817/ADN2818provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver.The ADN2817/ADN2818 have many optional features available through an I2C interface. For example, the user can read back the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER.The ADN2817/ADN2818 are available in a compact 5 mm × 5 mm, 32-lead, lead frame chip scale package.ApplicationsSONET OC-1, OC-3, OC-12, OC-48, and all associated FEC ratesFibre Channel, 2× Fibre Channel, GbE, HDTV, and othersWDM transpondersRegenerators/repeatersTest equipmentData Sheet, Rev. A, 8/08