Specification	DS25BR440TSQ/NOPB

Applications	LVDS
Current - Supply	162 mA
Delay Time	400 ps
Mounting Type	Surface Mount
Number of Channels	4
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	LVDS
Package / Case	40-WFQFN Exposed Pad
Signal Conditioning	Output Pre-Emphasis, Input Equalization
Supplier Device Package	40-WQFN (6x6)
Type	ReDriver, Buffer
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

DS25BR440 Series

3.125-Gbps quad LVDS buffer with transmit pre-emphasis and receive equalization

Part	Supplier Device Package	Output	Signal Conditioning	Package / Case	Type	Current - Supply	Delay Time	Mounting Type	Number of Channels	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Applications
Texas Instruments DS25BR440TSQX/NOPB	40-WQFN (6x6)	LVDS	Input Equalization Output Pre-Emphasis	40-WFQFN Exposed Pad	Buffer ReDriver	162 mA	400 ps	Surface Mount	4	85 °C	-40 °C	3.6 V	3 V	LVDS
Texas Instruments DS25BR440TSQ/NOPB	40-WQFN (6x6)	LVDS	Input Equalization Output Pre-Emphasis	40-WFQFN Exposed Pad	Buffer ReDriver	162 mA	400 ps	Surface Mount	4	85 °C	-40 °C	3.6 V	3 V	LVDS

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 9.04
		10	$ 8.16
		25	$ 7.79
		100	$ 6.76
	Digi-Reel®	1	$ 9.04
		10	$ 8.16
		25	$ 7.79
		100	$ 6.76
	Tape & Reel (TR)	250	$ 6.46
		500	$ 5.89
		1250	$ 5.13
Texas Instruments	SMALL T&R	1	$ 6.92
		100	$ 5.64
		250	$ 4.43
		1000	$ 3.76

Description

General part information

DS25BR440 Series

The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR440 features two levels of transmit pre-emphasis (PE) and two levels of receive equalization (EQ). Both of these features compensate for interconnect losses and ultimately maximize noise margin. A loss-of-signal (LOS) circuit monitors each input channel and a uniqueLOSpin is asserted when no signal is detected at that input.

Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device return losses, reduce component count and further minimize board space.

Documents

Technical documentation and resources

3.125 Gbps Quad LVDS Buffer w/ Transmit Pre-Emphasis and Receive Equalization datasheet (Rev. B)

Data sheet