Integrated Circuits (ICs)

HV509K6-G

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Microchip Technology

SHIFT REGISTER, HV509, SERIAL TO PARALLEL, 1 ELEMENT, 16 -BIT, 32 PINS, QFN

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DocumentsHV509 Datasheet Datasheet

Integrated Circuits (ICs)

HV509K6-G

Active

Microchip Technology

SHIFT REGISTER, HV509, SERIAL TO PARALLEL, 1 ELEMENT, 16 -BIT, 32 PINS, QFN

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DocumentsHV509 Datasheet Datasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	HV509K6-G

Function	Serial to Parallel
Logic Type	Shift Register
Mounting Type	Surface Mount
Number of Bits per Element	16
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Push-Pull
Package / Case	32-VFQFN Exposed Pad
Supplier Device Package	32-QFN (5x5)
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	2 V

HV509 Series

16-Channel S-P Converter with HV Backplane Driver and Push-Pull Outputs

Part	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Logic Type	Number of Bits per Element	Function	Number of Elements	Package / Case	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type
Microchip Technology HV509K6-G-M932	5.5 V	2 V	32-QFN (5x5)	Shift Register	16	Serial to Parallel	1	32-VFQFN Exposed Pad	Push-Pull	125 °C	-40 °C	Surface Mount
Microchip Technology HV509K6-G	5.5 V	2 V	32-QFN (5x5)	Shift Register	16	Serial to Parallel	1	32-VFQFN Exposed Pad	Push-Pull	125 °C	-40 °C	Surface Mount

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	1	$ 2.89
		25	$ 2.41
		100	$ 2.18
Microchip Direct	TRAY	1	$ 2.89
		25	$ 2.41
		100	$ 2.18
		1000	$ 2.12
		5000	$ 2.10

Description

General part information

HV509 Series

The HV509 is a 200V, 16-channel serial to parallel converter. The high voltage outputs and the backplane driver are designed to source and sink ±1.0mA.

The high voltage outputs are controlled by a 16-bit serial shift register, followed by a 16-bit latch. Data is shifted through the shift registers during the low to high clock transition. A data output buffer is provided for cascading multiple devices. Data is transferred to the 16-bit latch when a logic level low is applied to the LE input. Data is stored in the latch when LE is high. Output states are controlled by the data in the latch and by the POL pin.