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TSSOP (DGG)
Integrated Circuits (ICs)

V62/04715-01XE

Active
Texas Instruments

ENHANCED PRODUCT 3.3-V ABT 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

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Search across all available documentation for this part.

DocumentsAdvanced Bus Interface Logic Selection GuideUnderstanding and Interpreting Standard-Logic Data Sheets (Rev. C)+14
TSSOP (DGG)
Integrated Circuits (ICs)

V62/04715-01XE

Active
Texas Instruments

ENHANCED PRODUCT 3.3-V ABT 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsAdvanced Bus Interface Logic Selection GuideUnderstanding and Interpreting Standard-Logic Data Sheets (Rev. C)+14

Technical Specifications

Parameters and characteristics for this part

SpecificationV62/04715-01XE
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case6.1 mm
Package / Case0.24 in
Package / Case56-TFSOP
Supplier Device Package56-TSSOP
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]2.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 2000$ 2.77
Texas InstrumentsLARGE T&R 1$ 4.48
100$ 3.92
250$ 2.75
1000$ 2.22

Description

General part information

SN74LVTH16543-EP Series

The SN74LVTH16543 is a 16–bit registered transceiver designed for low–voltage (3.3–V) VCCoperation, but with the capability to provide a TTL interface to a 5–V system environment. This device can be used as two 8–bit transceivers or one 16–bit transceiver. Separate latch–enable (LEABorLEBA) and output–enable (OEABorOEBA) inputs are provided for each register to permit independent control in either direction of data flow.

The A–to–B enable (CEAB) input must be low to enter data from A or to output data from B. IfCEABis low andLEABis low, the A–to–B latches are transparent; a subsequent low–to–high transition ofLEABputs the A latches in the storage mode. WithCEABandOEABboth low, the 3–state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using theCEBA,LEBA, andOEBAinputs.

Active bus–hold circuitry is provided to hold unused or floating data inputs at a valid logic level.