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Technical Specifications
Parameters and characteristics for this part
| Specification | FDC6320C |
|---|---|
| Configuration | N and P-Channel |
| Current - Continuous Drain (Id) @ 25°C | 220 mA, 120 mA |
| Drain to Source Voltage (Vdss) | 25 V |
| FET Feature | Logic Level Gate |
| Gate Charge (Qg) (Max) @ Vgs | 0.4 nC |
| Input Capacitance (Ciss) (Max) @ Vds | 9.5 pF |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 150 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | TSOT-23-6, SOT-23-6 Thin |
| Power - Max [Max] | 700 mW |
| Rds On (Max) @ Id, Vgs | 4 Ohm |
| Supplier Device Package | SuperSOT™-6 |
| Technology | MOSFET (Metal Oxide) |
| Vgs(th) (Max) @ Id | 1.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Bulk | 1256 | $ 0.24 | |
| 1256 | $ 0.24 | |||
Description
General part information
FDC6320C Series
These dual N & P Channel logic level enhancement mode field effec transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors.
Documents
Technical documentation and resources