FDC6320C Series

Dual N & P Channel Digital FET 25V

Catalog

Dual N & P Channel Digital FET 25V

Part	Drain to Source Voltage (Vdss)	Gate Charge (Qg) (Max) @ Vgs	Operating Temperature [Min]	Operating Temperature [Max]	Vgs(th) (Max) @ Id	Power - Max [Max]	FET Feature	Technology	Package / Case	Current - Continuous Drain (Id) @ 25°C	Input Capacitance (Ciss) (Max) @ Vds	Mounting Type	Rds On (Max) @ Id, Vgs	Supplier Device Package	Configuration
ON Semiconductor FDC6320C	25 V	0.4 nC	-55 °C	150 °C	1.5 V	700 mW	Logic Level Gate	MOSFET (Metal Oxide)	SOT-23-6 Thin TSOT-23-6	120 mA 220 mA	9.5 pF	Surface Mount	4 Ohm	SuperSOT™-6	N and P-Channel
ON Semiconductor FDC6320C	25 V	0.4 nC	-55 °C	150 °C	1.5 V	700 mW	Logic Level Gate	MOSFET (Metal Oxide)	SOT-23-6 Thin TSOT-23-6	120 mA 220 mA	9.5 pF	Surface Mount	4 Ohm	SuperSOT™-6	N and P-Channel

Catalog

Dual N & P Channel Digital FET 25V

Key Features

• N-Ch 25 V, 0.22 A, RDS(ON) = 5 Ω @ VGS= 2.7 V.

• P-Ch 25 V, -0.12 A, RDS(ON) = 13 Ω @ VGS= -2.7 V.

• Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th)< 1.5 V.

• Gate-Source Zener for ESD ruggedness. >6kV Human Body Model.

• Replace NPN & PNP digital transistors.

Description

These dual N & P Channel logic level enhancement mode field effec transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors.