ADS61B23IRHBR
Active1-CHANNEL SINGLE ADC PIPELINED 80MSPS 12-BIT PARALLEL/SERIAL/LVDS 32-PIN VQFN EP T/R
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ADS61B23IRHBR
Active1-CHANNEL SINGLE ADC PIPELINED 80MSPS 12-BIT PARALLEL/SERIAL/LVDS 32-PIN VQFN EP T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | ADS61B23IRHBR |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | LVDS - Parallel, Parallel |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 1 |
| Number of Bits | 12 bits |
| Number of Inputs | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 32-VFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 80 M |
| Supplier Device Package | 32-VQFN (5x5) |
| Voltage - Supply, Analog [Max] | 3.6 V |
| Voltage - Supply, Analog [Min] | 3 V |
| Voltage - Supply, Digital [Max] | 3.6 V |
| Voltage - Supply, Digital [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 3000 | $ 30.49 | |
| Texas Instruments | LARGE T&R | 1 | $ 37.24 | |
| 100 | $ 33.11 | |||
| 250 | $ 27.21 | |||
| 1000 | $ 24.34 | |||
Description
General part information
ADS61B23 Series
ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.
ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability.
Documents
Technical documentation and resources