
AD9257TCPZ-65-CSL
ActiveOCTAL, 14-BIT, 65 MSPS SERIAL LVDS 1.8 V ANALOG-TO-DIGITAL CONVERTER
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AD9257TCPZ-65-CSL
ActiveOCTAL, 14-BIT, 65 MSPS SERIAL LVDS 1.8 V ANALOG-TO-DIGITAL CONVERTER
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Technical Specifications
Parameters and characteristics for this part
| Specification | AD9257TCPZ-65-CSL |
|---|---|
| Architecture | Pipelined |
| Configuration | ADC |
| Data Interface | LVDS - Serial, SPI |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 8 |
| Number of Bits | 14 |
| Number of Inputs | 16 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 64-WFQFN Exposed Pad, CSP |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | Internal |
| Sampling Rate (Per Second) | 65 M |
| Supplier Device Package | 64-LFCSP (9x9) |
| Voltage - Supply, Analog [Max] | 1.9 V |
| Voltage - Supply, Analog [Min] | 1.7 V |
| Voltage - Supply, Digital [Max] | 1.9 V |
| Voltage - Supply, Digital [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 493.15 | |
| 10 | $ 459.77 | |||
Description
General part information
AD9257S Series
The AD9257S-CSL is an octal, 14-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and low voltage, positive emitter-coupled logic (LVPECL)-/ CMOS-/low voltage differential signaling (LVDS)-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes 1 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9257S-CSL is available in an RoHS-compliant, 64-lead lead frame chip scale package (LFCSP). The device is specified over the −55°C to +125°C temperature range. This product is protected by a U.S. patent. Additional application and technical information can be found in the Commercial Space Products Program brochure and the AD9257 data sheet.PRODUCT HIGHLIGHTSSmall Footprint. Eight ADCs are contained in a small, space-saving package.Low Power of 55 mW/Channel at 65 MSPS with Scalable Power Options.Ease of Use. A DCO is provided that operates at frequencies of up to 455 MHz and supports double data rate (DDR) operation.User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.Pin Compatible with the AD9637 (12-Bit Octal ADC).APPLICATIONSLow Earth orbit (LEO) space payloadsQuadrature and diversity radio receiverOptical imaging
Documents
Technical documentation and resources