Integrated Circuits (ICs)

SN74LVTH573PWR

Active

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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Search across all available documentation for this part.

DocumentsPower-Up Behavior of Clocked Devices (Rev. B)Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)+16

Integrated Circuits (ICs)

SN74LVTH573PWR

Active

Texas Instruments

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsPower-Up Behavior of Clocked Devices (Rev. B)Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)+16

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVTH573PWR

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Delay Time - Propagation	2.9 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-TSSOP
Package / Case [x]	0.173 in
Package / Case [y]	4.4 mm
Supplier Device Package	20-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVTH573-EP Series

Enhanced Product 3.3-V Abt Octal Transparent D-Type Latches With 3-State Outputs

Part	Package / Case	Package / Case	Package / Case	Independent Circuits	Delay Time - Propagation	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Circuit [custom]	Circuit [custom]	Logic Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Package / Case [y]	Package / Case [y]	Package / Case [x]
Texas Instruments SN74LVTH573NSR	20-SOIC	0.209 "	5.3 mm	1	2.9 ns	Surface Mount	85 °C	-40 °C	20-SO	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State
Texas Instruments SN74LVTH573RGYR	20-VFQFN Exposed Pad			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-VQFN (3.5x4.5)	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State
Texas Instruments SN74LVTH573ZQNR	20-VFBGA			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-BGA MICROSTAR JUNIOR (4x3)	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State
Texas Instruments SN74LVTH573DWRE4	20-SOIC			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-SOIC	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	0.295 in	7.5 mm
Texas Instruments SN74LVTH573DBR	20-SSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-SSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State
Texas Instruments SN74LVTH573DWR	20-SOIC			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-SOIC	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	0.295 in	7.5 mm
Texas Instruments SN74LVTH573PW	20-TSSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-TSSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	4.4 mm		0.173 in
Texas Instruments SN74LVTH573IPWREP	20-TSSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-TSSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	4.4 mm		0.173 in
Texas Instruments SN74LVTH573PWG4	20-TSSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-TSSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	4.4 mm		0.173 in
Texas Instruments SN74LVTH573PWR	20-TSSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-TSSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	4.4 mm		0.173 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Arrow	N/A	2000	$ 0.39
		4000	$ 0.37
Digikey	Cut Tape (CT)	1	$ 1.55
		10	$ 0.98
		25	$ 0.83
		100	$ 0.66
		250	$ 0.57
		500	$ 0.52
		1000	$ 0.48
	Digi-Reel®	1	$ 1.55
		10	$ 0.98
		25	$ 0.83
		100	$ 0.66
		250	$ 0.57
		500	$ 0.52
		1000	$ 0.48
	Tape & Reel (TR)	2000	$ 0.44
		4000	$ 0.41
		6000	$ 0.39
		10000	$ 0.38
		14000	$ 0.37
		20000	$ 0.36
Texas Instruments	LARGE T&R	1	$ 0.68
		100	$ 0.52
		250	$ 0.39
		1000	$ 0.28

Description

General part information

SN74LVTH573-EP Series

These octal latches are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

Documents

Technical documentation and resources

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

Logic Guide (Rev. AB)

Selection guide

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note

Live Insertion

Application note

LVT Family Characteristics (Rev. A)

Application note

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

Application note

SN74LVTH573PWR

Deep-Dive with AI

SN74LVTH573PWR

Deep-Dive with AI

Technical Specifications

SN74LVTH573-EP Series

Pricing

Description

SN74LVTH573-EP Series

Documents

Power-Up Behavior of Clocked Devices (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

SN54LVTH573, SN74LVTH573 datasheet (Rev. H)

Input and Output Characteristics of Digital Integrated Circuits

Implications of Slow or Floating CMOS Inputs (Rev. E)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Understanding Advanced Bus-Interface Products Design Guide

TI IBIS File Creation, Validation, and Distribution Processes

LVT-to-LVTH Conversion

LOGIC Pocket Data Book (Rev. B)

Advanced Bus Interface Logic Selection Guide

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Logic Guide (Rev. AB)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Live Insertion

LVT Family Characteristics (Rev. A)

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

SN74LVTH573-EP Series