Integrated Circuits (ICs)

SN74LVTH573ZQNR

Obsolete

Texas Instruments

LATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN BGA MICROSTAR JUNIOR T/R

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Integrated Circuits (ICs)

SN74LVTH573ZQNR

Obsolete

Texas Instruments

LATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN BGA MICROSTAR JUNIOR T/R

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Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVTH573ZQNR

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Delay Time - Propagation	2.9 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-VFBGA
Supplier Device Package	20-BGA MICROSTAR JUNIOR (4x3)
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVTH573-EP Series

Enhanced Product 3.3-V Abt Octal Transparent D-Type Latches With 3-State Outputs

Part	Package / Case	Package / Case	Package / Case	Independent Circuits	Delay Time - Propagation	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Circuit [custom]	Circuit [custom]	Logic Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Package / Case [y]	Package / Case [y]	Package / Case [x]
Texas Instruments SN74LVTH573NSR	20-SOIC	0.209 "	5.3 mm	1	2.9 ns	Surface Mount	85 °C	-40 °C	20-SO	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State
Texas Instruments SN74LVTH573RGYR	20-VFQFN Exposed Pad			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-VQFN (3.5x4.5)	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State
Texas Instruments SN74LVTH573ZQNR	20-VFBGA			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-BGA MICROSTAR JUNIOR (4x3)	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State
Texas Instruments SN74LVTH573DWRE4	20-SOIC			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-SOIC	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	0.295 in	7.5 mm
Texas Instruments SN74LVTH573DBR	20-SSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-SSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State
Texas Instruments SN74LVTH573DWR	20-SOIC			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-SOIC	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	0.295 in	7.5 mm
Texas Instruments SN74LVTH573PW	20-TSSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-TSSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	4.4 mm		0.173 in
Texas Instruments SN74LVTH573IPWREP	20-TSSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-TSSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	4.4 mm		0.173 in
Texas Instruments SN74LVTH573PWG4	20-TSSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-TSSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	4.4 mm		0.173 in
Texas Instruments SN74LVTH573PWR	20-TSSOP			1	2.9 ns	Surface Mount	85 °C	-40 °C	20-TSSOP	2.7 V	3.6 V	8	8	D-Type Transparent Latch	64 mA	32 mA	Tri-State	4.4 mm		0.173 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Bulk	606	$ 0.50

Description

General part information

SN74LVTH573-EP Series

These octal latches are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

Documents

Technical documentation and resources

No documents available