
SPC564B74L7B8E0X
Active32-BIT POWER ARCHITECTURE MCU FOR AUTOMOTIVE BODY AND GATEWAY APPLICATIONS

SPC564B74L7B8E0X
Active32-BIT POWER ARCHITECTURE MCU FOR AUTOMOTIVE BODY AND GATEWAY APPLICATIONS
Technical Specifications
Parameters and characteristics for this part
| Specification | SPC564B74L7B8E0X |
|---|---|
| Connectivity | CANbus, LINbus, UART/USART, SPI |
| Core Processor | e200z4d |
| Core Size | 32-Bit |
| Data Converters | 5x12b, A/D 27x10b |
| EEPROM Size | 64 K |
| Grade | Automotive |
| Mounting Type | Surface Mount |
| Number of I/O | 147 |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 176-LQFP |
| Peripherals | DMA, PWM, POR, WDT |
| Program Memory Size | 3 MB |
| Program Memory Type | FLASH |
| Qualification | AEC-Q100 |
| RAM Size | 192 K |
| Speed | 120 MHz |
| Supplier Device Package | 176-LQFP (24x24) |
| Voltage - Supply (Vcc/Vdd) [Max] | 5.5 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 12.99 | |
Description
General part information
SPC564B74L7 Series
The SPC564Bxx and SPC56ECxx is a new family of next generation microcontrollers built on the Power Architecture embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device.
The SPC564Bxx and SPC56ECxx family expands the range of the SPC560B microcontroller family. It provides the scalability needed to implement platform approaches and delivers the performance required by increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of the SPC564Bxx and SPC56ECxx automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original Power Architecture user instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high performance processing optimized for low power consumption. It also capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.
Documents
Technical documentation and resources