Specification	SN74V3690-6PEU

Access Time	4.5 ns
Bus Directional	Uni-Directional
Current - Supply (Max) [Max]	40 mA
Data Rate	166 MHz
Expansion Type	Width, Depth
Function	Synchronous
FWFT Support	True
Memory Size	1.125 M
Mounting Type	Surface Mount
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Package / Case	128-LQFP
Programmable Flags Support	True
Retransmit Capability	True
Supplier Device Package	128-LQFP
Voltage - Supply [Max]	3.45 V
Voltage - Supply [Min]	3.15 V

SN74V3690 Series

32768 x 36 Synchronous FIFO Memory

Part	Current - Supply (Max) [Max]	Package / Case	Memory Size	Function	Data Rate	Bus Directional	Operating Temperature [Max]	Access Time	Mounting Type	Supplier Device Package	Expansion Type	Voltage - Supply [Max]	Voltage - Supply [Min]
Texas Instruments SN74V3690-10PEU	40 mA	128-LQFP	1.125 M	Synchronous	100 MHz	Uni-Directional	70 °C	6.5 ns	Surface Mount	128-LQFP	Depth Width	3.45 V	3.15 V
Texas Instruments SN74V3690-7PEU	40 mA	128-LQFP	1.125 M	Synchronous	133.3 MHz	Uni-Directional	70 °C	5 ns	Surface Mount	128-LQFP	Depth Width	3.45 V	3.15 V
Texas Instruments SN74V3690-6PEU	40 mA	128-LQFP	1.125 M	Synchronous	166 MHz	Uni-Directional	70 °C	4.5 ns	Surface Mount	128-LQFP	Depth Width	3.45 V	3.15 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	1	$ 40.84
		10	$ 37.88
		25	$ 36.53
		72	$ 35.62
		144	$ 31.21
		288	$ 30.35
Texas Instruments	JEDEC TRAY (5+1)	1	$ 38.65
		100	$ 34.35
		250	$ 28.24
		1000	$ 25.26

Description

General part information

SN74V3690 Series

The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:

Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.

Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or 9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus matching (BM) during the master-reset cycle.

Documents

Technical documentation and resources

Datasheet

Power-Dissipation Calculations for TI FIFO Products (Rev. A)

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note