Specification	NLV14094BDG

Function	Serial to Parallel
Grade	Automotive
Logic Type	Shift Register
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Tri-State
Package / Case	16-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Qualification	AEC-Q100
Supplier Device Package	16-SOIC
Voltage - Supply [Max]	18 V
Voltage - Supply [Min]	3 V

MC14094B Series

8-Bit Storage/Shift Register with Three-State Outputs

Part	Operating Temperature [Min]	Operating Temperature [Max]	Number of Bits per Element	Package / Case	Package / Case [x]	Package / Case [y]	Function	Supplier Device Package	Logic Type	Number of Elements	Output Type	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Grade	Qualification	Package / Case	Package / Case
ON Semiconductor MC14094BDG	-55 °C	125 °C	8	16-SOIC	0.154 in	3.9 mm	Serial to Parallel	16-SOIC	Shift Register	1	Tri-State	Surface Mount	18 V	3 V
ON Semiconductor NLV14094BDR2G	-55 °C	125 °C	8	16-SOIC	0.154 in	3.9 mm	Serial to Parallel	16-SOIC	Shift Register	1	Tri-State	Surface Mount	18 V	3 V	Automotive	AEC-Q100
ON Semiconductor MC14094BCPG	-55 °C	125 °C	8	16-DIP			Serial to Parallel	16-PDIP	Shift Register	1	Tri-State	Through Hole	18 V	3 V			0.3 in	7.62 mm
ON Semiconductor MC14094BDTR2G	-55 °C	125 °C	8	16-TSSOP	0.173 in	4.4 mm	Serial to Parallel	16-TSSOP	Shift Register	1	Tri-State	Surface Mount	18 V	3 V
ON Semiconductor NLV14094BDG	-55 °C	125 °C	8	16-SOIC	0.154 in	3.9 mm	Serial to Parallel	16-SOIC	Shift Register	1	Tri-State	Surface Mount	18 V	3 V	Automotive	AEC-Q100
ON Semiconductor MC14094BFELG	-55 °C	125 °C	8	16-SOIC			Serial to Parallel	16-SOEIAJ	Shift Register	1	Tri-State	Surface Mount	18 V	3 V			0.209 "	5.3 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

MC14094B Series

The MC14094B combines an 8-stage shift register with a data latch for each stage and a three-state output from each latch.Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is for use in high-speed cascaded systems. The QSoutput data is shifted on the following negative clock transition for use in low-speed cascaded systems.Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high.Outputs of the eight data latches are controlled by three-state buffers which are placed in the high-impedance state by a logic Low on Output Enable.