
MC14094BDTR2G
ActiveSHIFT REGISTER/LATCH SINGLE 8-BIT SERIAL TO SERIAL/PARALLEL 16-PIN TSSOP T/R

MC14094BDTR2G
ActiveSHIFT REGISTER/LATCH SINGLE 8-BIT SERIAL TO SERIAL/PARALLEL 16-PIN TSSOP T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | MC14094BDTR2G |
|---|---|
| Function | Serial to Parallel |
| Logic Type | Shift Register |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Tri-State |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 16-TSSOP |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.25 | |
| 10 | $ 0.75 | |||
| 25 | $ 0.62 | |||
| 100 | $ 0.49 | |||
| 250 | $ 0.42 | |||
| 500 | $ 0.38 | |||
| 1000 | $ 0.35 | |||
| Digi-Reel® | 1 | $ 1.25 | ||
| 10 | $ 0.75 | |||
| 25 | $ 0.62 | |||
| 100 | $ 0.49 | |||
| 250 | $ 0.42 | |||
| 500 | $ 0.38 | |||
| 1000 | $ 0.35 | |||
| Tape & Reel (TR) | 2500 | $ 0.32 | ||
| 5000 | $ 0.30 | |||
| 7500 | $ 0.28 | |||
| 12500 | $ 0.27 | |||
| 17500 | $ 0.27 | |||
| 25000 | $ 0.26 | |||
| Newark | Each (Supplied on Full Reel) | 1 | $ 0.36 | |
| 3000 | $ 0.35 | |||
| 6000 | $ 0.33 | |||
| 12000 | $ 0.30 | |||
| 18000 | $ 0.28 | |||
| 30000 | $ 0.27 | |||
| ON Semiconductor | N/A | 1 | $ 0.28 | |
Description
General part information
MC14094B Series
The MC14094B combines an 8-stage shift register with a data latch for each stage and a three-state output from each latch.Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is for use in high-speed cascaded systems. The QSoutput data is shifted on the following negative clock transition for use in low-speed cascaded systems.Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high.Outputs of the eight data latches are controlled by three-state buffers which are placed in the high-impedance state by a logic Low on Output Enable.
Documents
Technical documentation and resources