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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AVC16373GQLR |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low [custom] | 12 mA |
| Current - Output High, Low [custom] | 12 mA |
| Delay Time - Propagation | 7.2 ns |
| Independent Circuits | 2 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 56-VFBGA |
| Supplier Device Package | 56-BGA Microstar Junior (7x4.5) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.4 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74AVC16373 Series
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.
This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation.
The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
Documents
Technical documentation and resources
