Specification	CDCLVD2104RHDT

Differential - Input:Output [custom]	True
Differential - Input:Output [custom]	True
Frequency - Max [Max]	800 MHz
Input	LVDS, LVCMOS, LVPECL
Mounting Type	Surface Mount
Number of Circuits	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	LVDS
Package / Case	28-VFQFN Exposed Pad
Ratio - Input:Output	1:4
Supplier Device Package	28-VQFN (5x5)
Type	Fanout Buffer (Distribution)
Voltage - Supply [Max]	2.625 V
Voltage - Supply [Min]	2.375 V

CDCLVD2104 Series

Low jitter, dual 1:4 universal-to-LVDS buffer

Part	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Ratio - Input:Output	Supplier Device Package	Output	Input	Mounting Type	Number of Circuits	Type	Package / Case	Frequency - Max [Max]	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments CDCLVD2104RHDT			2.375 V	2.625 V	1:4	28-VQFN (5x5)	LVDS	LVCMOS LVDS LVPECL	Surface Mount	2	Fanout Buffer (Distribution)	28-VFQFN Exposed Pad	800 MHz	85 °C	-40 °C
Texas Instruments CDCLVD2104RHDR			2.375 V	2.625 V	1:4	28-VQFN (5x5)	LVDS	LVCMOS LVDS LVPECL	Surface Mount	2	Fanout Buffer (Distribution)	28-VFQFN Exposed Pad	800 MHz	85 °C	-40 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 10.66
		10	$ 9.63
		25	$ 9.18
		100	$ 7.97
	Digi-Reel®	1	$ 10.66
		10	$ 9.63
		25	$ 9.18
		100	$ 7.97
	Tape & Reel (TR)	250	$ 5.54
Texas Instruments	SMALL T&R	1	$ 8.16
		100	$ 6.65
		250	$ 5.23
		1000	$ 4.43

Description

General part information

CDCLVD2104 Series

The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2104 is specifically designed for driving 50-transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

Documents

Technical documentation and resources

Dual 1:4 Low Additive Jitter LVDS Buffer datasheet (Rev. A)

Data sheet