CDCLVD2104RHDR
ActiveLOW JITTER, DUAL 1:4 UNIVERSAL-TO-LVDS BUFFER
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CDCLVD2104RHDR
ActiveLOW JITTER, DUAL 1:4 UNIVERSAL-TO-LVDS BUFFER
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CDCLVD2104RHDR |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 800 MHz |
| Input | LVDS, LVCMOS, LVPECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVDS |
| Package / Case | 28-VFQFN Exposed Pad |
| Ratio - Input:Output | 1:4 |
| Supplier Device Package | 28-VQFN (5x5) |
| Type | Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 2.625 V |
| Voltage - Supply [Min] | 2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 8.88 | |
| 10 | $ 8.03 | |||
| 25 | $ 7.65 | |||
| 100 | $ 6.64 | |||
| 250 | $ 6.35 | |||
| 500 | $ 5.79 | |||
| 1000 | $ 5.04 | |||
| Digi-Reel® | 1 | $ 8.88 | ||
| 10 | $ 8.03 | |||
| 25 | $ 7.65 | |||
| 100 | $ 6.64 | |||
| 250 | $ 6.35 | |||
| 500 | $ 5.79 | |||
| 1000 | $ 5.04 | |||
| Tape & Reel (TR) | 3000 | $ 4.85 | ||
| Texas Instruments | LARGE T&R | 1 | $ 6.80 | |
| 100 | $ 5.54 | |||
| 250 | $ 4.36 | |||
| 1000 | $ 3.70 | |||
Description
General part information
CDCLVD2104 Series
The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2104 is specifically designed for driving 50-transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.
Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.
Documents
Technical documentation and resources