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24-SOIC
Integrated Circuits (ICs)

SN74LVT8996DW

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Texas Instruments

3.3-V ABT 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVER

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24-SOIC
Integrated Circuits (ICs)

SN74LVT8996DW

Active
Texas Instruments

3.3-V ABT 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVER

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVT8996DW
Logic TypeAddressable Scan Ports
Mounting TypeSurface Mount
Number of Bits [custom]10
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case24-SOIC
Package / Case [custom]7.5 mm
Package / Case [custom]0.295 in
Supplier Device Package24-SOIC
Supply Voltage [Max]3.6 V
Supply Voltage [Min]2.7 VDC

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 75$ 12.53
Texas InstrumentsTUBE 1$ 12.53
100$ 10.94
250$ 8.44
1000$ 7.55

Description

General part information

SN74LVT8996-EP Series

The 'LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETMdevices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

These devices are functionally equivalent to the 'ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to interface to 5-V masters and/or targets.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.