Discrete Semiconductor Products

FDMS3620S

Obsolete

ON Semiconductor

ASYMMETRIC DUAL N-CHANNEL POWERTRENCH® POWERSTAGE MOSFET, 25V

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsDatasheet

Discrete Semiconductor Products

FDMS3620S

Obsolete

ON Semiconductor

ASYMMETRIC DUAL N-CHANNEL POWERTRENCH® POWERSTAGE MOSFET, 25V

Deep-Dive with AI

DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	FDMS3620S

Configuration	2 N-Channel (Dual) Asymmetrical
Drain to Source Voltage (Vdss)	25 V
FET Feature	Logic Level Gate
Gate Charge (Qg) (Max) @ Vgs [Max]	26 nC
Input Capacitance (Ciss) (Max) @ Vds [Max]	1570 pF
Mounting Type	Surface Mount
Operating Temperature [Max]	150 °C
Operating Temperature [Min]	-55 °C
Package / Case	8-PowerTDFN
Power - Max [Max]	1 W
Rds On (Max) @ Id, Vgs	4.7 mOhm
Supplier Device Package	Power56
Technology	MOSFET (Metal Oxide)
Vgs(th) (Max) @ Id	2 V

FDMS3620S Series

Asymmetric Dual N-Channel PowerTrench® PowerStage MOSFET, 25V

Part	Technology	Package / Case	Configuration	Mounting Type	FET Feature	Drain to Source Voltage (Vdss)	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package	Rds On (Max) @ Id, Vgs	Power - Max [Max]	Gate Charge (Qg) (Max) @ Vgs [Max]	Input Capacitance (Ciss) (Max) @ Vds [Max]	Vgs(th) (Max) @ Id
ON Semiconductor FDMS3620S	MOSFET (Metal Oxide)	8-PowerTDFN	2 N-Channel (Dual) Asymmetrical	Surface Mount	Logic Level Gate	25 V	-55 °C	150 °C	Power56	4.7 mOhm	1 W	26 nC	1570 pF	2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

FDMS3620S Series

This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronousSyncFET (Q2) have been designed to provide optimal power efficiency.

Documents

Technical documentation and resources