DS90C3202VS/NOPB
Active3.3V 8 MHZ TO 135 MHZ DUAL FPD-LINK RECEIVER
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DS90C3202VS/NOPB
Active3.3V 8 MHZ TO 135 MHZ DUAL FPD-LINK RECEIVER
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Technical Specifications
Parameters and characteristics for this part
| Specification | DS90C3202VS/NOPB |
|---|---|
| Data Rate | 945 Mbps |
| Mounting Type | Surface Mount |
| Number of Drivers/Receivers [custom] | 10 |
| Number of Drivers/Receivers [custom] | 0 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 128-TQFP |
| Protocol | LVDS, FPD-Link |
| Type | Receiver |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3.15 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 90 | $ 4.73 | |
| 270 | $ 4.48 | |||
| 450 | $ 4.02 | |||
| 2250 | $ 3.22 | |||
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 4.87 | |
| 100 | $ 3.97 | |||
| 250 | $ 3.12 | |||
| 1000 | $ 2.65 | |||
Description
General part information
DS90C3202 Series
The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3202 is designed to interface between the digital video processor and the display device using the low-power, low-EMI LVDS (Low Voltage Differential Signaling) interface. The DS90C3202 converts up to ten LVDS data streams back into 70 bits of parallel LVCMOS/LVTTL data. The receiver can be programmed with rising edge or falling edge clock. Optional wo-wire serial programming allows fine tuning in development and production environments. With an input clock at 135 MHz, the maximum transmission rate of each LVDS line is 945 Mbps, for an aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This allows the dual 10-bit LVDS Receiver to support resolutions up to HDTV.
The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3202 is designed to interface between the digital video processor and the display device using the low-power, low-EMI LVDS (Low Voltage Differential Signaling) interface. The DS90C3202 converts up to ten LVDS data streams back into 70 bits of parallel LVCMOS/LVTTL data. The receiver can be programmed with rising edge or falling edge clock. Optional wo-wire serial programming allows fine tuning in development and production environments. With an input clock at 135 MHz, the maximum transmission rate of each LVDS line is 945 Mbps, for an aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This allows the dual 10-bit LVDS Receiver to support resolutions up to HDTV.
Documents
Technical documentation and resources