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SN74ALS137AN

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Texas Instruments

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

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PDIP (N)
Integrated Circuits (ICs)

SN74ALS137AN

Active
Texas Instruments

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ALS137AN
Circuit1 x 3:8
Current - Output High, Low [custom]400 µA
Current - Output High, Low [custom]8 mA
Independent Circuits1
Mounting TypeThrough Hole
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
Supplier Device Package16-PDIP
TypeDecoder/Demultiplexer
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V
Voltage Supply SourceSingle Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 25$ 3.60
125$ 3.12
250$ 2.96
625$ 2.82
Texas InstrumentsTUBE 1$ 5.24
100$ 4.59
250$ 3.22
1000$ 2.59

Description

General part information

SN74ALS137A Series

The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/demultiplexers with latches on the three address inputs. When the latch-enable () input is low, the devices act as decoders/demultiplexers. Whengoes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long asremains high. The output-enable controls (G1 and G2\) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2\ is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.

The SN54ALS137A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS137A and SN74AS137 are characterized for operation from 0°C to 70°C.

The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/demultiplexers with latches on the three address inputs. When the latch-enable () input is low, the devices act as decoders/demultiplexers. Whengoes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long asremains high. The output-enable controls (G1 and G2\) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2\ is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.