MC100EPT21MNR4G
ActiveTRANSLATOR, 2 INPUT, 2.25 NS, 3 V TO 3.6 V, 8 PINS, DFN-EP
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MC100EPT21MNR4G
ActiveTRANSLATOR, 2 INPUT, 2.25 NS, 3 V TO 3.6 V, 8 PINS, DFN-EP
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC100EPT21MNR4G |
|---|---|
| Channel Type | Unidirectional |
| Channels per Circuit | 1 |
| Input Signal | LVPECL, CML, LVDS |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Signal | LVCMOS, LVTTL |
| Output Type | Non-Inverted |
| Package / Case | 8-VFDFN Exposed Pad |
| Supplier Device Package | 8-DFN (2x2) |
| Translator Type | Mixed Signal |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
MC100EPT21 Series
The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.The VBBoutput allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, VBBoutput tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, VBBoutput is connected through a resistor to each input pin. If used, the VBBpin should be bypassed to VCCvia a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBBfor a single-ended direct connection.
Documents
Technical documentation and resources
